Integrated circuits, principally on account of the ever increasing complexity and the ever higher speed, have the problem that the users of the integrated circuits, more precisely the users of the modules and devices containing the integrated circuits, are often no longer able to identify or to eliminate the causes of improper functioning of the integrated circuits and/or of the systems containing the integrated circuits.
For this reason, so-called emulators have been developed for particularly complex integrated circuits, for example for microprocessors and microcontrollers, with the aid of which emulators, during the normal operation of an integrated circuit, internal states and sequences in the integrated circuit, such as, for example, register contents, memory contents and/or addresses, data, control signals transferred via internal, or external lines or bus systems, etc., can be observed and altered as desired.
During an emulation of an integrated circuit, the latter would generally be removed from the system containing it and be replaced by a special circuit, the special circuit containing the integrated circuit itself that is to be tested or a particular version of the integrated circuit (a so-called bond-out version having additional terminals for observing internal states and operations).
The above-mentioned integrated circuit disclosed in DE 101 00 344.7 was based on the object of providing a particularly suitable and simple possibility of emulation for complex integrated circuits by virtue of the integrated circuit comprising, in addition to a first circuit part, for example a processor or controller part, a second circuit part, which is necessary or useful for the emulation thereof, alongside of the first circuit part on the same silicon wafer.
During the fabrication of the integrated circuit, an exposure mask is used for each exposure plane, patterns for fabricating a first circuit part of the integrated circuit and patterns for fabricating a second circuit part thereof being situated jointly on said exposure mask, in which case, during the fabrication of a variant which does not contain the second circuit part, that part of the exposure mask which serves for fabricating the second circuit part is covered and, during the fabrication of a variant of the integrated circuit which has the second circuit part, the relevant part of the exposure mask remains uncovered.
The known procedure is explained in more detail with reference to the accompanying diagrammatic FIGS. 6A, 6B, 6C, 7 and 8.
FIGS. 6A, 6B and 6C firstly show, in diagrammatic plan view, three different integrated circuits such as are known from the abovementioned DE 101 00 344.7. In accordance with FIG. 6A, a first integrated circuit IC1 has a first circuit part 1 and a second circuit part 21. As mentioned, the first circuit part 1 is a processor circuit, for example, and the second circuit part 21 is an emulator circuit which is used for the emulation of the first circuit part 1 but is integrated-separately from the latter along one side (the upper side in FIG. 6A) of the first circuit part 1. Connecting lines between the first circuit part 1 and the second circuit part 21 are provided but are not illustrated for the sake of simplicity.
A variant of the integrated circuit that is designated by IC2 is illustrated diagrammatically in FIG. 6B. Here, the second circuit part designated by the numeral 22 is integrated separately from the first circuit part 1, however, along two sides thereof. In the two variants shown in FIGS. 6A and 6B, the first circuit part 1 and the second circuit part 21 and 22, respectively, are neither interleaved in one another nor do their respective regions overlap.
FIG. 6C diagrammatically illustrates a variant of the integrated circuit that is designated by IC3, which does not have a second circuit part. The procedure in mass production is usually such that very many integrated circuits IC3 in accordance with FIG. 6C and a few integrated circuits IC1 or IC2 in accordance with FIG. 6A or FIG. 6B are fabricated on a wafer. In FIGS. 6A–6C, connecting lines of the integrated circuit are designated by 3 and terminal points are designated by 4.
FIGS. 7 and 8 show that, during the method for fabricating the known integrated circuit, for each exposure plane with an exposure mask 10, which has regions for the first circuit part 1 and in addition for the second circuit part 2, it is possible to fabricate an integrated circuit IC1 in accordance with FIG. 6A and an integrated circuit IC3 in accordance with FIG. 6C, that is to say without a first circuit part.
For this purpose, regions of the exposure mask 10 are either not covered (FIG. 7) or are covered (FIG. 8) by displaceable sections S1, S3 of a diaphragm S having the sections S1, S2, S3 and S4. The arrows m illustrate that the sections S1 and S3 of the diaphragm S are displaceable in this way.
One problem in the case of the known method outlined above is that a relatively large distance has to be complied with in each case between the first mask region serving for the production of the first circuit part and the mask region serving for the production of the second circuit part, which distance unfortunately cannot be made arbitrarily small on account of the unsharpness during the imaging of the diaphragm sections S1, S3. Therefore, too much space on the wafer is given away during the mass production of an integrated circuit in accordance with FIG. 8.